SCLI=0, IICRST=0, SCLO=0, CLO=0, SDAI=0, ICE=0, SOWP=0, SDAO=0
I2C Bus Control Register 1
| SDAI | SDA Line Monitor 0 (0): SDAn line is low. 1 (1): SDAn line is high. |
| SCLI | SCL Line Monitor 0 (0): SCLn line is low. 1 (1): SCLn line is high. |
| SDAO | SDA Output Control/Monitor 0 (0): (Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low. 1 (1): (Read)The RIIC has released the SDAn pin./ (Write)The RIIC releases the SDAn pin. |
| SCLO | SCL Output Control/Monitor 0 (0): (Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low. 1 (1): (Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin. |
| SOWP | SCLO/SDAO Write Protect 0 (0): Enables a value to be written in SCLO bit and SDAO bit. 1 (1): Disables a value to be written in SCLO bit and SDAO bit. |
| CLO | Extra SCL Clock Cycle Output 0 (0): Does not output an extra SCL clock cycle. 1 (1): Outputs an extra SCL clock cycle. |
| IICRST | I2C Bus Interface Internal Reset Note:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information). 0 (0): Releases the RIIC reset or internal reset. 1 (1): Initiates the RIIC reset or internal reset. |
| ICE | I2C Bus Interface Enable 0 (0): Disable (SCLn and SDAn pins in inactive state) 1 (1): Enable (SCLn and SDAn pins in active state) |